1. Field of the Invention
The present invention relates generally to semiconductor processing and more specifically to a method of sealing a semiconductor substrate and to a semiconductor chip resulting from such a method.
2. Discussion of Related Art
The manufacture of a semiconductor chip involves the formation of metal members on a substrate. These members usually include bond pads, metal lines and a guard ring surrounding the bond pads and the metal lines. The substrate and the metal lines are sealed from the ingress of moisture with an undulating sealing layer which rises over the members and falls into gaps between the members. Holes are etched into the sealing layer to expose areas on the bond pads where metal leads are connected to for electrically connecting the chip to another device.
The members oppose one another, causing stray capacitance to build up between the members which is estimated according to the equation: ##EQU1## where K is the dielectric constant of the material between the members, .epsilon. is the permittivity of free space, A is the exposed area between the members area of a plate, and d is the distance between the members.
As device dimensions decrease and the members are becoming closer to one another, the distance d in the above equation decreases, resulting in a higher stray capacitance. The material of the sealing layer usually has a dielectric constant K which is fairly high, typically above 7.0, thus increasing stray capacitance and enhancing the problem of delay in reaction time of the circuit. A high stray capacitance is undesirable because it causes resistance-capacitance (RC) delay in the reaction time of an underlying circuit.
A method is thus required wherein a semiconductor chip can be manufactured with a material in the gaps which has a low dielectric constant K while maintaining a good seal against the ingress of moisture.